> characteristic times of electronic signals are restricted by so-called parasitic capacitances, and parasitic capacitances in general are proportional to the length of the connection
> modern CPUs use so-called “dynamic branch prediction”
These two mostly served to distract me and break up the reading flow of the page, and I initially thought they had been erroneously truncated.
This next one is straight-up nonsensical because it's missing context:
> Overall, these effects seem to compensate each other, and main memory access latencies of an x64 desktop box, and an M4 Apple SoC happen to be in the same ballpark of about 200-300 CPU cycles.
Which effects?
If the author is reading this, I would advise you to either remove these, or try to be more careful about what sentences you decide to pull out in this way to make sure that they communicate something useful by themselves. Ideally something that reflects the overall theme of the surrounding paragraphs.
The illustrations attached also seem to have nothing to do with the text but that's probably not a big deal.