From the GitHub page:
> It is a Gameboy Advance from a parallel universe where RISC-V existed in 2001. A love letter to the handheld consoles from my childhood, and a 3AM drunk text to the technology that powered them.
The GBA was designed around having no cache. With a few exceptions (such as Internal RAM, Video RAM, IO registers, BIOS, OAM, Palettes), everything goes out to an external bus. Going out to an external bus with no cache will basically slow you down to 80s computer speeds. Fetching instructions from the cartridge ends up being around twice as fast as a GBC.
The way around that is using a cache, and sequentially fetching multiple words. Sequential fetches can be made faster, increasing throughput, and that can hide the latency if enough instructions/data gets cached.
I wonder how this system is designed, is it going to the memory bus for all fetches, or does it use a cache?
Oh this is Luke Wren’s work. He’s an ASIC design engineer at Raspberry Pi. Amazing project, I love it!
This guy also designed DVI/HDMI from RP2040:
https://github.com/Wren6991/PicoDVI
The design was taped out on the first wafer.space run (see
https://github.com/wafer-space/ws-run1) but I have not heard if it actually worked or not.
The programmable scanline-buffer-based rendering pipeline described in the PDF is worth a read for fans of such things.
The author of this is one of the greatest minds of our time. While doing this is cool, he also designed the Hazard3 core in the RP2350 as well as the QSPI unit in it -- the only memory-mapped QSPI unit I've encountered so far that I've not been able to crash or hang.
Is the greatest challenge in adopting this new hardware architecture the technology itself, or the lack of an existing developer ecosystem and software toolchains?
i love the "hardware from an alternate universe" projects.
I'm surprised to see that it's OK that he has opensource AHB/APB stuff in it--I'd avoided learning them too much about them assuming that they were ARM proprietary.